Hilbert-Schmidt Operators vs. Integrable Systems of Elliptic Calogero-Moser Type III. The Heun Case

The Heun equation can be rewritten as an eigenvalue equation for an ordinary differential operator of the form $-d^2/dx^2+V(g;x)$, where the potential is an elliptic function depending on a coupling vector $g\in{\mathbb R}^4$. Alternatively, this operator arises from the $BC_1$ specialization of the $BC_N$ elliptic nonrelativistic Calogero-Moser system (a.k.a. the Inozemtsev system). Under suitable restrictions on the elliptic periods and on $g$, we associate to this operator a self-adjoint operator $H(g)$ on the Hilbert space ${\mathcal H}=L^2([0,\omega_1],dx)$, where $2\omega_1$ is the real period of $V(g;x)$. For this association and a further analysis of $H(g)$, a certain Hilbert-Schmidt operator ${\mathcal I}(g)$ on ${\mathcal H}$ plays a critical role. In particular, using the intimate relation of $H(g)$ and ${\mathcal I}(g)$, we obtain a remarkable spectral invariance: In terms of a coupling vector $c\in{\mathbb R}^4$ that depends linearly on $g$, the spectrum of $H(g(c))$ is invariant under arbitrary permutations $\sigma(c)$, $\sigma\in S_4$

A note on the Gauss decomposition of the elliptic Cauchy matrix

Explicit formulas for the Gauss decomposition of elliptic Cauchy type matrices are derived in a very simple way. The elliptic Cauchy identity is an immediate corollary.Comment: 5 page

Lattice sites of ion-implanted Li in diamond

Published in: Appl. Phys. Lett. 66 (1995) 2733-2735 citations recorded in [Science Citation Index] Abstract: Radioactive Li ions were implanted into natural IIa diamonds at temperatures between 100 K and 900 K. Emission channelling patterns of a-particles emitted in the nuclear decay of 8Li (t1/2 = 838 ms) were measured and, from a comparison with calculated emission channelling and blocking effects from Monte Carlo simulations, the lattice sites taken up by the Li ions were quantitatively determined. A fraction of 40(5)% of the implanted Li ions were found to be located on tetrahedral interstitial lattice sites, and 17(5)% on substitutional sites. The fractions of implanted Li on the two lattice sites showed no change with temperature, indicating that Li diffusion does not take place within the time window of our measurements.

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.2009 Asian Test Symposium, 23-26 November 2009, Taichung, Taiwa

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.2008 17th Asian Test Symposium (ATS 2008), 24-27 November 2008, Sapporo, Japa

First-principle study of excitonic self-trapping in diamond

We present a first-principles study of excitonic self-trapping in diamond. Our calculation provides evidence for self-trapping of the 1s core exciton and gives a coherent interpretation of recent experimental X-ray absorption and emission data. Self-trapping does not occur in the case of a single valence exciton. We predict, however, that self-trapping should occur in the case of a valence biexciton. This process is accompanied by a large local relaxation of the lattice which could be observed experimentally.Comment: 12 pages, RevTex file, 3 Postscript figure

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi